With the advent of electronic design automation (EDA), the design of complex hardware systems no longer begins with a hardware circuit diagram. Instead, circuit design typically begins with a software program that describes the behavior or functionality of the hardware system. In one exemplary approach, the behavior or functionality of an electronic circuit design may be described using a hardware-description language (HDL) (e.g., VHDL, Verilog, or other such language). Circuit designers direct behavioral synthesis tools to generate alternate architectures by modifying constraints (e.g., clock period, number and type of data path elements, and desired number of clock cycles). Behavioral synthesis tools convert the HDL program into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.
An example of HDL source code, shown in Table 1 below, declares three variables (a, b, and c) that are arrays. Each array contains 1024 8-bit words. The code first declares a “subtype” to define the type of each element in the array. The code then defines a “type” to represent the array itself. Finally, the variables are declared, each variable representing an array.
TABLE 1SUBTYPE word IS unsigned (7 DOWNTO 0);TYPE array_type IS ARRAY (integer RANGE <> ) of word;VARIABLE a, b, c: array_type (0 to 1023);
Generally, the variables can be accessed using loops, such as the loop shown below in Table 2. When an array is mapped to memory, each element in the array is mapped to a memory location. For example, a(0) maps to address 0, a(1) maps to address 1, and a(1023) maps to address 1023.
TABLE 2FOR i IN 0 TO 15 LOOP a(i) = b (i) * c(i) + 4;END LOOP;
After the designer completes the HDL source code, the designer may run the source code through the synthesis tool. A typical synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the area and latency of the circuit to determine whether the current loop configuration is acceptable. If the loop configuration is not acceptable, the designer typically returns to an editor, re-edits the source code to unroll or pipeline loops, and runs the source code through the synthesis tool again. Such a technique for modifying the design is time consuming and inefficient. Moreover, the designer cannot easily visualize how the loop configuration changes the design while modifying the source code.
RTL methodologies have previously sufficed to simulate and design simple hardware blocks but today fall far short in many ways. Design complexity of new digital signal processing (DSP) applications has outpaced traditional RTL methods. As such, designers have moved to C++ or Matlab® to quickly validate their algorithms. While this higher abstraction has helped system verification, it has also widened the technology gap between the system designers using high-level languages and the hardware designers who hand-code the RTL.
Designs have evolved from single- or multi-block functional units into large systems that include embedded cores and complex hardware implementing proprietary compute-intensive algorithms. Despites these advances, engineers still use iterative RTL methods that involve manual steps such as micro-architecture definition, handwritten RTL, and area/speed optimization through RTL synthesis. This process is slow and error-prone. Moreover, since both the micro-architecture and destination technology characteristics are hard-coded into the RTL description, the whole notion of RTL reuse or retargeting becomes impractical for real applications.